1. Field of Invention
The present invention relates to a malfunction-free electro-optical device, a clock signal adjusting method therefor, a clock signal adjusting circuit therefor, a producing method therefor, and electronic equipment using the electro-optical device.
2. Description of Related Art
A conventional electro-optical device, for example, a conventional active matrix liquid crystal display device includes a device substrate on which a switching device is provided at each of pixel electrodes arranged like a matrix, an opposing substrate on which color filters are formed, and liquid crystal filled between the substrates. In such a configuration, when a scanning signal is applied to a switching device through a scanning line, the switching device is conducted. When an image signal is applied to a pixel electrode through a data line during the switching device is in such a conducting state, a predetermined amount of electric charge is stored in a liquid crystal layer between the pixel electrode and an opposing electrode (or common electrode). Even when the switching device is turned off after the charge is stored, the stored charge is maintained in the case that the resistance of the liquid crystal layer is sufficiently high. Controlling an amount of stored charge by driving each switching device in this manner causes a change in the alignment of crystal liquid molecules at each pixel. This enables the display to indicate predetermined information.
At that time, the operation of storing charge in the liquid crystal layer of each pixel requires only part of processing time. Thus, a time division multiplexing driving method, according to which each of scanning lines and data lines is shared by a plurality of pixels, is implemented by first sequentially selecting scanning lines by means of a scanning line driving circuit, and second sequentially selecting one or more data lines by means of a data line driving circuit in a scanning line selecting time, and third sampling image signals and supplying the sampled image signals to the selected data lines.
Incidentally, generally, the scanning line driving circuit and the data line driving circuit are constituted by shift register circuits. According to a signal transferred by each of these shift register circuits, the scanning line driving circuit performs a vertical scanning operation, while the data line driving circuit performs a horizontal scanning operation.
Meanwhile, the scanning line driving circuit and the data line driving circuit may be formed on the aforementioned device substrate, in addition to an image display area including the scanning lines, data lines and switching devices. In such a case, a thin film transistor (hereunder referred to as TFT) is usually used as an active device constituting each of the scanning line driving circuit and the data line driving circuit.
Incidentally, in the case of some process for forming TFTs, there is variation in threshold voltage of a TFT. Especially, in the case of using a glass substrate as the device substrate, there is a large variation in the threshold voltage of a TFT.
On the other hand, each of the shift register circuits includes series-connected unit circuits, each of which includes a clocked inverter and a latch circuit. Each of the shift register circuits sequentially shifts a start pulse according to a clock signal and an inverted clock signal.
However, as described above, there is variation in threshold voltages of TFTs of the shift registers. Thus, when there is a certain difference between the threshold voltage and a designed value, each of the shift registers malfunctions. The operating speed of a TFT varies with the electric current value of an ON-current thereof. Thus, when there is a certain difference between the electric current value of the ON-current and a designed value, each of the shift registers malfunctions.
In such cases, even when the image display area normally operates, the liquid crystal panel should be rejected as a defective on the whole. Consequently, the conventional device has a drawback in that the yield of the liquid crystal panel is reduced.
The present invention is accomplished in view of the aforementioned circumstances. Accordingly, an object of the present invention is to provide a clock signal adjusting method and circuit, which can prevent the shift registers from malfunctioning, and to provide an electro-optical device and electronic equipment, to which the clock signal adjusting method and circuit are applied. Further, another object of the present invention is to provide an electro-optical devices producing method that can enhance the yield of the electro-optical devices when such devices are produced.
To achieve such objects, according to the present invention, there is provided a method of adjusting a clock signal in an electro-optical device having a display portion, which has a plurality of scanning lines, a plurality of data lines, and pixels provided respectively corresponding to intersections between the scanning lines and the data lines, and also having a shift register that sequentially shifts a start pulse according to a clock signal and an inverted clock signal. This method can be employed in the electro-optical device adapted to generate each of signals, which are supplied to the plurality of scanning lines and the plurality of data lines, according to each output signal of the shift register, and that the phases of the clock signal and the inverted clock signal to be supplied to the shift register are adjusted. Moreover, this method of the present invention comprises the steps of detecting a threshold voltage of each of transistors of the shift register, and adjusting the relative phases of the clock signal and the inverted clock signal according to the detected threshold voltage.
The turning on and off of the transistors of the shift register are controlled according to the clock signal and the inverted clock signal. It is determined by the threshold voltage of a transistor and a voltage supplied to the control terminal thereof whether the transistor is turned on or off. When the threshold voltage has a value that is higher or lower than a target value, the timing of switching between the on and off of the transistor shifts from intended timing. Even in such a case, according to the method of the present invention, the relative phases of the clock signal and the inverted clock signal are adjusted according to the threshold voltage of the transistor. Thus, the shift register can be normally operated.
Incidentally, preferably, at the step of detecting the threshold voltage of the transistor, a threshold voltage of a test transistor produced by the same manufacturing process as that of manufacturing the transistors of the shift register is measured. Moreover, the threshold voltage of each of transistors is detected according to a result of the measurement. The threshold voltages of the transistors produced by the same manufacturing process are equal to each other. Thus, the threshold voltage of the transistor of the shift register can be known by measuring the threshold voltage of such a test transistor. The present invention eliminates the necessity for directly measuring the threshold voltage of the transistor of the shift register. The threshold voltage of the transistor of the shift register can easily be detected by placing the test transistor in such a manner as to facilitate the measurement of the threshold voltage thereof.
Further, when the transistors of the shift register are a P-channel TFT and an N-channel TFT, preferably, at the step of measuring the threshold voltage, a first threshold voltage of the P-channel TFT and a second threshold voltage of the N-channel TFT are measured. Moreover, preferably, at the step of adjusting the phases of the clock signal and the inverted clock signal, the relative phases are adjusted according to the first and second threshold voltages. Thus, the relative phases can be adjusted according to the characteristics of the two kinds of transistors. Even when the threshold voltages of the P-channel TFT and the N-channel TFT are deviated from target values, the on/off timing of each of the TFTs can be adjusted to normal timing. Consequently, the shift register can be prevented from malfunctioning.
Furthermore, preferably, at the step of adjusting the phases, the relative phases of a leading edge of the clock signal and a trailing edge of the inverted clock signal are adjusted according to the first threshold voltage. In this case, the phase of the trailing edge of the inverted clock signal may be advanced and delayed with respect to the leading edge of the clock signal. Conversely, the phase of the leading edge of the clock signal may be advanced and delayed with respect to the trailing edge of the inverted clock signal.
Additionally, at the step of adjusting the phases, preferably, the relative phases of the trailing edge of the clock signal and the leading edge of the inverted clock signal are adjusted according to the second threshold voltage. In this case, the phase of the leading edge of the inverted clock signal may be advanced and delayed with respect to the trailing edge of the clock signal. Conversely, the phase of the trailing edge of the clock signal may be advanced and delayed with respect to the leading edge of the inverted clock signal.
Next, according to another aspect of the present invention, there is provided another method for use in an electro-optical device, which comprises the aforementioned prerequisites, and which further comprises the steps of detecting the threshold voltage and ON-current of each of transistors of the shift register, and adjusting the relative phases of the clock signal and the inverted clock signal according to the detected threshold voltage and ON-current.
When the magnitude of the ON-current of the transistor is large, the signal has high slew rate. Conversely, when the magnitude of the ON-current is low, the signal has low slew rate. Therefore, the on/off timing of the transistor of the shift register depends upon the ON-current. According to the present invention, the relative phases of the clock signal and the inverted clock signal are adjusted according not only to the threshold voltage of the transistor but also to the ON-current. Thus, when the magnitude of the ON-current of the transistor is deviated from the design target value according to the manufacturing process thereof, the shift register can be normally operated.
Incidentally, at the step of detecting a threshold voltage and an ON-current of each of transistors, preferably, the threshold voltage and ON-current of the test transistor produced is measured by the same manufacturing process as that of manufacturing the transistors of the shift register. Moreover, preferably, the threshold voltage and ON-current of each of the transistors is detected according to a result of the measurement. The present invention eliminates the need for directly measuring the threshold voltage of the transistor of the shift register. The threshold voltage and ON-current of the transistor of the shift register can easily be detected by placing the test transistor in such a manner as to facilitate the measurement of the threshold voltage thereof.
Further, when the transistors of the shift register are a P-channel TFT and an N-channel TFT, preferably, at the step of measuring the threshold voltage, the first threshold voltage and ON-current of the P-channel TFT and the second threshold voltage and ON-current of the N-channel TFT are measured. Moreover, preferably, at the step of adjusting the phases of the clock signal and the inverted clock signal, the relative phases are adjusted according to the first and second threshold voltages and the first and second ON-currents. Thus, the relative phases can be adjusted according to the characteristics of the two kinds of transistors. Even when the threshold voltages and ON-currents of the P-channel TFT and the N-channel TFT are deviated from target values, the on/off timing of each of the TFTs can be adjusted to normal timing. Consequently, the shift register can be prevented from malfunctioning.
Further, at the step of adjusting the phases of a leading edge of the clock signal and a trailing edge of the inverted clock signal, preferably, the relative phases can be adjusted according to the first threshold voltage and the first ON-current. In addition, at the step of adjusting the phases of a trailing edge of the clock signal and a leading edge of the inverted clock signal, preferably, the relative phases can be adjusted according to the second threshold voltage and the second ON-current.
Next, according to another aspect of the present invention, there is provided a clock signal adjusting circuit for use in an electro-optical device comprising a display portion, which has a plurality of scanning lines, a plurality of data lines, and pixels provided respectively corresponding to the intersections between the scanning lines and the data lines, and also having a shift register for sequentially shifting a start pulse according to a clock signal and an inverted clock signal. This clock signal adjusting circuit can be employed in the electro-optical device adapted to generate each of signals, which are supplied to the plurality of scanning lines and the plurality of data lines, according to each output signal of the shift register, and that the phases of the clock signal and the inverted clock signal to be supplied to the shift register are adjusted. Moreover, this clock signal adjusting circuit of the present invention comprises a first phase adjusting portion for adjusting the relative phases of a leading edge of the clock signal and a trailing edge of the inverted clock signal according to a threshold voltage of a transistor of the shift register, and a second phase adjusting portion for adjusting the relative phases of a trailing edge of the clock signal and a leading edge of the inverted clock signal according to the threshold voltage of a transistor of the shift register.
According to this clock signal adjusting circuit of the present invention, the relative phases of the clock signal and the inverted clock signal can be adjusted according to the threshold voltage of the transistor. Thus, even when the threshold voltage of the transistor is largely deviated from the design target value, such a shift register can be driven without malfunctioning.
Further, when the transistors of the shift register are a P-channel TFT and an N-channel TFT, preferably, the clock signal adjusting circuit of the present invention further comprises a first threshold voltage detecting portion that detects a first threshold voltage of the P-channel TFT, and a second threshold voltage detecting portion that detects a second threshold voltage detecting portion that detects a second threshold voltage of the N-channel TFT. Moreover, preferably, the first phase adjusting portion adjusts the relative phases of the leading edge of the clock signal and the trailing edge of the inverted clock signal according to the first threshold voltage, while the second phase adjusting portion adjusts the relative phase of the trailing edge of the clock signal and the leading edge of the inverted clock signal according to the second threshold voltage. According to the clock signal adjusting circuit of the present invention, the relative phases can be adjusted according to the characteristics of the two kinds of transistors of the shift register. Thus, the on/off timing of each of TFTs can be adjusted to the normal timing.
Incidentally, when the shift register normally shifts a start pulse in the case that an absolute value of the first threshold voltage is equal to a first reference voltage value and an absolute value of the second threshold voltage is equal to a second reference voltage value, preferably, the first phase adjusting portion delays the trailing edge of the inverted clock signal from the leading edge of the clock signal in the case that the absolute value of the first threshold voltage is lower than the first reference value and that the absolute value of the second threshold voltage is higher than the second reference voltage value. Furthermore, when the shift register normally shifts a start pulse in the case that an absolute value of the first threshold voltage is equal to a first reference voltage value and that an absolute value of the second threshold voltage is equal to a second reference voltage value, preferably, the first phase adjusting portion delays the trailing edge of the inverted clock signal from the leading edge of the clock signal in the case that the absolute value of the first threshold voltage is higher than the first reference value and that the absolute value of the second threshold voltage is lower than the second reference voltage value.
Additionally, preferably, at least the first and second threshold voltage detecting portions are formed on the same substrate on which the shift register is formed. Furthermore, it is preferable that the first threshold voltage detecting portion has and uses a P-channel TFT formed in the same process as a process, in which the P-channel TFT of the shift register is formed, to thereby detect the first threshold voltage, and that the first threshold voltage detecting portion has and uses an N-channel TFT formed in a same process as a process, in which the N-channel TFT of the shift register is formed, to thereby detect the second threshold voltage.
Next, according to another aspect of the present invention, there is provided another clock signal adjusting circuit for use in an electro-optical device, which has the aforementioned requisites and further comprises a first phase adjusting portion that adjusts the relative phases of a leading edge of the clock signal and a trailing edge of the inverted clock signal according to the threshold voltage and ON-current of a transistor of the shift register, and a second phase adjusting portion that adjusts the relative phases of a trailing edge of the clock signal and a leading edge of the inverted clock signal according to the threshold voltage and ON-current of a transistor of the shift register.
According to this clock signal adjusting circuit of the present invention, the relative phases of the clock signal and the inverted clock signal are adjusted according not only to the threshold voltage of the transistor but also to the ON-current. Thus, when the magnitude of the ON-current of the transistor is deviated from the design target value according to the manufacturing process thereof, the shift register can be normally operated.
Further, when the transistors of the shift register are a P-channel TFT and an N-channel TFT, preferably, the clock signal adjusting circuit further comprises a first threshold voltage detecting portion that detects a first threshold voltage of the P-channel TFT, a second threshold voltage detecting portion that detects a second threshold voltage of the N-channel TFT, a first ON-current detecting portion that detects a first ON-current of the P-channel TFT, and a second ON-current detecting portion that detects a second ON-current detecting portion that detects a second ON-current of the N-channel TFT. Moreover, preferably, the first phase adjusting portion adjusts the relative phases of the leading edge of the clock signal and the trailing edge of the inverted clock signal according to the first threshold voltage and ON-current, while the second phase adjusting portion adjusts the relative phases of the trailing edge of the clock signal and the leading edge of the inverted clock signal according to the second threshold voltage and ON-current.
Furthermore, the first phase adjusting portion may increase a delay time of the trailing edge of the inverted clock signal with respect to the leading edge of the clock signal as the first ON-current increases. Further, the second phase adjusting portion may increase a delay time of the leading edge of the clock signal with respect to the trailing edge of the inverted clock signal as the second ON-current increases.
Additionally, in the clock signal adjusting circuit for use in an electro-optical device, preferably, the shift register is constituted by cascade-connecting a plurality of unit circuits. Moreover, preferably, each of the unit circuits comprises a first inverter being supplied with an input signal of the unit circuit and a latch circuit that comprises a second inverter, which is operative to invert an output signal of the first inverter and to output a resultant signal as an output signal of the unit circuit, and a third inverter, which is operative to invert an output signal of the second inverter and to supply the inverted signal to an input terminal of the second inverter. Furthermore, preferably, the first inverter is configured so that the first inverter has a first P-channel TFT, a second P-channel TFT, a first N-channel TFT, and a second N-channel TFT, which are serially series-connected between a positive power supply and a negative power supply, that an output signal of the first inverter is fetched from a connecting point between the second P-channel TFT and the first N-channel TFT, that a gate of the second P-channel TFT is connected to the gate of the first N-channel TFT, that an input signal to a corresponding one of the plurality of unit circuits is supplied to a connecting point between the second P-channel TFT and the first N-channel TFT, that a clock signal is supplied to a gate of the first P-channel TFT of each odd-numbered one of the plurality of unit circuits, that an inverted clock signal is supplied to a gate of the second N-channel TFT of each odd-numbered one of the plurality of unit circuits, and that an inverted clock signal is supplied to a gate of the first P-channel TFT of each even-numbered one of the plurality of unit circuits, that an clock signal is supplied to a gate of the second N-channel TFT of each even-numbered one of the plurality of unit circuits.
Next, according to the present invention, there is provided an electro-optical device of the present invention that comprises a display portion having a plurality of scanning lines, a plurality of data lines, and pixels provided respectively corresponding to the intersections between the plurality of scanning lines and the plurality of data lines, a shift register that sequentially shifts a start pulse according to a clock signal and an inverted clock signal, a driving portion that generates signals to be supplied to the plurality of scanning lines and the plurality of data lines, and the aforementioned clock signal adjusting circuit. According to this electro-optical device of the present invention, almost no malfunction of the shift register occurs. Consequently, the picture quality of a displayed image can be enhanced.
Further, according to the present invention, there is provided electronic equipment that uses the aforementioned electro-optical device as display means. Examples of this electronic equipment are a hand-portable telephone set, a video projector, and a view-finder of a camcorder.
Next, according to the present invention, there is provided a method of producing an electro-optical device having the following requisites, that is, a display panel, which has a display portion including a plurality of scanning lines, a plurality of data lines, and pixels respectively provided correspondingly to the intersections between the scanning lines and the data lines, and also has a driving portion that drives the display portion by using a shift register, and also having a clock signal generating circuit enabled to generate a clock signal and an inverted clock signal, which are supplied to the shift register, and to adjust the relative phases of the clock signal and the inverted clock signal. Further, this method comprises the steps of manufacturing the display panel, measuring a threshold voltage of each of transistors of the shift register of the manufactured display panel, and adjusting the relative phases of the clock signal and the inverted clock signal according to the measured threshold voltage.
According to this method of the present invention, when the display panel is produced, the relative phases of the clock signal and the inverted clock signal can be adjusted even in the case that the threshold voltage of each of the transistors is largely deviated from the design target value. Thus, the shift register can be normally operated. Consequently, even a display panel, which has hitherto been treated as a defective, can be treated as a quality item. Therefore, the yield of the display panel can be considerably enhanced. Consequently, the manufacturing cost of the electro-optical device can be reduced.